In recent years, computers (data processing devices) used for servers and the like usually adopt a configuration in which plural CPUs (Central Processing Units) are connected by buses. In such a configuration, a CPU that carries a data transmitting/receiving device is adopted to transmit and receive data through a bus.
The bus is a transmission path group having plural transmission paths. Each of the transmission paths is a differential transmission path (lane) having two transmission lines driven by differential drive. This lane of the differential transmission path is adapted to speeding up owing to less noise generation than the lane of single-end transmission path, although it requires two transmission lines for serial connection with a data width of 1 bit.
When the data transmitting/receiving device loaded in the CPU transmits data through a bus, data to be transmitted is divided for each lane and the divided data is serially transmitted. The data transmitting/receiving device usually adds an error-detecting code for error detection to the data to be transmitted so that the receiver end can detect an error caused at the data reception. A CRC (Cyclic Redundancy Check) has been widely used as an error-detecting code.
This error-detecting code is usually generated by using all of the data to be transmitted. For that reason, the receiver end generates an error-detecting code by using received data other than the error-detecting code and compares the generated error-detecting code (CRC code) with the received error-detecting code. As a result of this comparison, when the two error-detecting codes match, it is regarded in such a case that no error has occurred, and when the two error-detecting codes do not match, it is regarded in such a case that an error occurred. When the receiver end finds that an error has occurred, the receiver end discards the received data and requests the retransmission of the data to the transmitter end.
The data transmission between CPUs significantly influences the data processing speed of the CPU and the throughput of the data processing device (computer) loading the CPUs. For this reason, the requirement of the high-speed data transmission is significantly high. However as the transmission speed becomes higher, the influence of the noise also becomes greater. As a result, the requirement of stable operations becomes significantly high.
The above lanes can be independently operated. Therefore when a failure occurs in any of the lanes, degeneracy to stop the failed lane is performed. This is because it is highly probable that errors will occur in the data transmission in the failed lane.
The receiver end can detect an error in units of packets by using the error-detecting code. However, the receiver end cannot identify the lane in which the error occurred. For that reason, in the past, the lane in which a failure (error) occurred was identified by transmitting and receiving data (patterns) prepared in advance. The data prepared in advance is, for example, a PBRS (Pseudo Random Binary (bit) Sequence) pattern.
The transmission and reception of such data prepared in advance has to be performed after stopping the operation of the system (data processing device). The operation stoppage of the data processing device decreases the operation time of the data processing device, and thus blocks efficient operation of the data processing device. For that reason, it is important to identify the lane in which a failure (error) has occurred during the operations of the data processing device.
The waveform distortion of the data transmission in each lane, i.e., the influence of noise, is not always the same. It is possible for the data reception characteristics to be different in each lane due to the variation of the processes. For that reason, errors may be concentrated on a particular lane in which a failure has not occurred. In order to identify a lane with highly frequent error occurrences, it is desirable to have a mechanism to detect an error in units of lanes during the operations of the data processing device.
Technical documents for reference include Japanese Laid-open Patent Publication No. 2010-61606, Japanese Laid-open Patent Publication No. 2009-294853, and Japanese Laid-open Patent Publication No. 2010-11454.